An On-line Evolvable Hardware for Learning Finite-State Machine

The paper proposes an on-line evolvable hardware (EHW), called mimetic EHW. The task is to mimic a sequential circuit by observing its partial input/output sequences. The genetic algorithm (GA) is used to search for the circuit satisfying input/output sequences collected from the target circuit. The mimetic EHW consists of a custom microprocessor and a tness evaluator. The microprocessor is particularly designed for an execution of GA. The evaluator acts as a coprocessor, accelerating the tness evaluation which is a bottleneck of GA. The microprocessor and the evaluator are designed using the Verilog hardware description language (Verilog HDL), then realised on Xilinx XC4010 FPGAs. The result shows that, by using the state-of-the-art FPGA, the microprocessor combined with a parallel of 8 tness evaluators could perform 36 times faster then the software version running on a conventional computer (Pentium Pro with Linux OS).